When asked about what devices the Tessent tools address, Press said, “All devices need an RTL-based hierarchical DFT flow, this is especially true for complex devices such as AI/machine-learning applications. “Tessent works closely with the majority of leading silicon providers to develop silicon-proven cell-aware diagnosis and machine-learning technologies.” Finally, he noted that Tessent Operations embraces partnerships with ATE companies. “Tessent Safety also has a partnership with ARM to provide a safety island flow. Press added that Tessent Safety includes BIST Observation Scan Technology, that can execute LBIST tests five times faster when in system operation. “Our products are designed to handle huge and complex semiconductor designs, and Tessent includes all DFT functions under one tool with one database.” There is much more intent-driven automation, since DFT products share information between them, and DFT intent is passed up the plug-and-play hierarchical DFT structure. “DFT used to be disparate tools,” he said. Press elaborated on the Tessent approach to the three areas. The third targets operations with tools to help with silicon bring-up and tools that apply machine learning to production test results to improve product yield.
The second area addresses safety, with in-system test managers and automotive-grade pattern generation. First is DFT for logic insertion, mostly at RTL for BIST, embedded scan compression, scan, device-level DFT infrastructure, and on-chip clock controllers. “Tessent offers software products in three areas of semiconductor test,” according to Ron Press, technology enablement director, Tessent. Mentor, a Siemens Business, addresses silicon test and yield analysis with its Tessent product suite. Software also has a role to play, as do test accessories. Available products include high-performance ATE systems as well as instruments that can operate in standalone mode or augment existing ATE systems.
Vendors of test solutions are responding with technologies that boost productivity, while keeping costs under control. The increasing complexity of semiconductor devices is placing stringent demands on test.
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